Pentium® Pro Processor Design for Test and Debug

1 Its microarchitecture forms the basis of the company's future high-volume microprocessor portfolio. The initial design has also been augmented with enhancements such as MMX technology and compacted onto newer fabrication processes to create the Pentium II processor product line. 2 The original Pentium Pro processor design , known initially as the P6, introduced several performance features, including s register and flag renaming s speculative and out-of-order dispatch and execution of instructions s reordered memory access s multiple branch prediction s a full-speed second-level (L2) cache ac-cessed through a dedicated 72-bit backside bus s a 64-bit, transaction-oriented, pipelined front-side bus, which operates at GTL voltage levels and directly supports four-way multiprocessing systems The design was first implemented in Intel's proprietary 0.6-µm, four-metal Bi-CMOS process. The CPU die measured 683 mils (17.3 mm) on a side and contained 5.5 million transistors. Designers created two versions of the shipped product by combining the CPU with either a 15.5-million transistor , 256-Kbyte L2 cache or a 31-million transistor, 512-Kbyte L2 cache. In either case, the CPU and L2 cache dies were mounted in a 387-pin, dual-cavity, ceramic PGA package , with wire-bonded connections to the pad rings. The challenges associated with production test and debug on the processor were considerable, due to its tight release schedule , the enormous complexity of its circuit design and microarchitecture, and the complexity of the system platform. In addition to these issues, Intel's unique business requirement of simultaneously meeting very high production, performance, and test quality targets strongly influenced its design-for-test direction. This set of constraints limits Intel microprocessor design teams' ability to use DFT and test generation techniques (full or partial scan and scan-based BIST), which are commonly used in other microprocessors in the industry. 3-7 Within these constraints, the design team optimized the design for low die area, high performance, low power dissipa-tion, high test quality, and low test cost. Die area. Raw fab output is a function of wafer capacity and product die size. In addition to the die area impact on yield, more fabs must be built to ship a larger design, assuming a fixed quantity of product. An independent study has estimated that a die area increase of 15% in one particular Pentium processor design would have cost Intel the construction of a new multibillion-dollar fab. 8 For this reason, die area plays an overwhelming role in the economics of high-The need …